Welcome to ChipEleven’s Wiki #
The CPU core of ChipEleven’s first SOC adheres to the OpenPOWER 3.0B ISA spec and is known as PythonWatt.
The OpenPOWER specifications are currently somewhat incomplete. This wiki intends to help capture some information about OpenPOWER learned in the process of developing PythonWatt as well as some of the logistical details and mechanics surrounding the implementation of ChipEleven’s first SOC.
Hopefully future OpenPOWER ISA implementors find this Wiki helpful as well.
PythonWatt is to be a 4-core SMP capable CPU. The OpenPOWER docs are missing some information that is needed to implement a performant modern core, namely:
- XICs behaviors
- MMU with table walking behaviors
- Coherent Cache interface expectations
- OPAL API matching Linux POWERNV kernel
OpenPOWER is a fairly recent endeavor and more docs are sure to come, but in the meantime…
Referencing MicroWatt #
Support for the above features is on the roadmap for MicroWatt. MicroWatt however, currently does not synthesize well(it has some critical path blooming) resulting in a slow clock speed.
The PythonWatt developers are focused on delivering a fast core that synthesizes well and are in close communication with MicroWatt developers to ensure that PythonWatt’s behaviors are OpenPOWER compliant.